DRAM Addressing Capacity

Dynamic RAM is typically used in computers because it is cheaper than Static RAM.

Dynamic RAM must be periodically refreshed by an access to RAM or the data contained within the RAM cell decays.  Static RAM does not need refreshing, all it needs is a steady supply of power.  Computers typically had a method of refreshing the RAM, often tied to the video controller, which refreshes the screen fifty or sixty times per second.  Steve Wozniak for example used a unified memory architecture where the video controller circuitry would access the RAM 50-60 times per second, which was sufficiently reliable to keep the RAM contents from degrading.

Virtually all vintage home computers used discrete DRAM chips.  However, if you look at the printed circuit board of any old computer, you will see memory chips in columns of eight (or nine) chips.  Why is that?  This is because a DRAM chip typically holds one bit of data for each memory cell.  So you need eight chips to hold a byte.  By contrast, you only need one SRAM chip to hold a byte.  Despite the need for a refresh circuit and the extra space and complexity required to interface eight DRAM chips compared to one SRAM chip, DRAM was still so much cheaper that it was almost always used.

Vintage consoles more often used SRAM because it made their boards cheaper to manufacture, an important concern when you intend to sell millions of systems based on the same board design.  The Atari 2600 used 128 bytes of SRAM, but it was embedded within the RIOT chip.  The Atari 5200 used 16KB of DRAM chips, but it was based on the design of the Atari 8-bit computers.  The Colecovision uses 1KB of DRAM chips for CPU memory but also a 16KB SRAM chip for the video memory.  The NES uses 2KB SRAMs for CPU and PPU memory, but its sprite RAM uses embedded DRAM on the CPU.  The SNES uses DRAM throughout, which tends to cause the white stripe issue with its video due to the refresh signal.

In a system with a sixteen bit data bus, you need sixteen chips.  In this system, the CPU deals in two bytes (a word) at a time.  So the first eight chips hold one byte and the second eight chips hold the next byte.  An earlier IBM PC AT system has two banks of eighteen chips each (see parity below).  When fully populated, you will have a whopping 512KB of RAM.  Each socket uses a pair of 64Kb chips, one piggybacked on top of the other, for 128Kb.  So each row of chips provides 128KB.  The CPU sees a pair of rows in a 128Kx16bit configuration, but in real purposes you have 256x8bits.

IBM systems, except for the PCjr., use parity memory.  Parity memory uses a ninth DRAM chip for each eight DRAM chips.  The extra chip is not usable memory, it instead alerts the system to a memory error.

By the mid eighties, some companies were using four bit DRAMs.  Four bit DRAMs hold four times the bit capacity as a one bit DRAM.  So when you used to need eight chips to form a bank of eight bit DRAM, now you only need two chips.

One bit DRAMs typically have a marking on them like 4116 or 4164, denoting 16Kb and 64Kb parts, respectively.  (In this article, a "B" as in KB means byte and a "b" as in Kb means bit).  Four bit DRAMs have markings like 4416 and 4464 for the same respective parts.    They are also commonly shown as 16Kx1 and 16Kx4.

You can find 1Kb, 4Kb, 16Kb, 64Kb, 256Kb and even 1Mb DRAM chips.  You will not find 2Kb, 8Kb, 32Kb, 128Kb or 512Kb chips.  Why is that?  This is because of the way DRAM is addressed.  DRAM is addressed more in a matrix-fashion than a true linear fashion.  DRAM uses address lines just like SRAM and ROM chips, but fewer than you would expect.

SRAM can be had in virtually any power of two capacity.  1KB, 2KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 512KB and 1MB SRAM chips exist.  Many chips of the lower capacities can be found in NES and SNES cartridges.

A 64KB SRAM chip has sixteen address lines, but a 64Kb DRAM chip only has eight.  We all know that 2^16 = 64KB, right?  In order to get to 64Kb in a DRAM chip, you need the Row Access Strobe (RAS) and the Column Access Strobe (CAS) signals.  So, first you send a read or write via the address lines and RAS signal, then you send the read or write via the address lines and the CAS signal.  Since you are using eight bits twice to get to the correct memory cell, you get your sixteen address bits.  If you add a ninth address line to your chip, you will get eighteen bit addressing, which gives you 256Kb.  This is why there is no such thing as a 128Kb DRAM chip.